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A practical guide to semiconductor manufacturing from process control to yield modeling and experimental design. Page 1. Page Page Page Page Fundamentals. Interconnect[ edit ] Synthetic detail of a standard cell through four layers of planarized copper interconnect, down to the polysilicon pink , wells greyish and substrate green.
Historically, the metal wires have been composed of aluminum. In this approach to wiring often called subtractive aluminum , blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires.
Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes called "vias" in the insulating material and then depositing tungsten in them with a CVD technique; this approach is still used in the fabrication of many memory chips such as dynamic random-access memory DRAM , because the number of interconnect levels is small currently no more than four.
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor , the timing delay in the wiring has become so significant as to prompt a change in wiring material from aluminum to copper interconnect layer and a change in dielectric material from silicon dioxides to newer low-K insulators. This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps.
As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography.
Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP chemical-mechanical planarization is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three.
Wafer test[ edit ] The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index and extinction coefficient of photoresist and other coatings.
Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.
The proportion of devices on the wafer found to perform properly is referred to as the yield.
Process variation is one among many reasons for low yield. The machine marks each bad chip with a drop of dye.
Currently, electronic dye marking is possible if wafer test data is logged into a central computer database and chips are "binned" i. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging.
Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Usually, the fab charges for testing time, with prices in the order of cents per second.